1. Field of the Invention
This invention generally relates to computer systems and, more particularly, to integrated bus bridge designs for use in high performance computer systems. The invention also relates to arbitration mechanisms and to delayed transaction operations employed within laptop computer systems docked to expansion bases.
2. Background of the Invention
Computer architectures generally include a plurality of devices interconnected by one or more buses. For example, conventional computer systems typically include a CPU coupled through bridge logic to an external main memory. A main memory controller is thus typically incorporated within the bridge logic to generate various control signals for accessing the main memory. An interface to a high bandwidth local expansion bus, such as the Peripheral Component Interconnect (PCI) bus, may also be included as a portion of the bridge logic. Examples of devices which can be coupled to the local expansion bus include network interface cards, video accelerators, audio cards, SCSI adapters, telephony cards, etc. An older-style expansion bus may be supported through yet an additional bus interface to provide compatibility with earlier-version expansion bus adapters. Examples of such expansion buses include the Industry Standard Architecture (ISA) bus, also referred to as the AT bus, the Extended Industry Standard Architecture (EISA) bus, and the Microchannel Architecture (MCA) bus. Various devices may be coupled to this second expansion bus, including a fax/modem card, sound card, etc.
The bridge logic can link or interface more than simply the CPU bus, a peripheral bus such as a PCI bus, and the memory bus. In applications that are graphics intensive, a separate peripheral bus optimized for graphics related transfers may be supported by the bridge logic. A popular example of such a bus is the AGP (Advanced Graphics Port) bus. AGP is generally considered a high performance, component level interconnect optimized for three dimensional graphical display applications, and is based on a set of performance extensions or enhancements to PCI. AGP came about, in part, from the increasing demands placed on memory bandwidths for three dimensional renderings. AGP provided an order of magnitude bandwidth improvement for data transfers between a graphics accelerator and system memory. This allowed some of the three dimensional rendering data structures to be effectively shifted into main memory, relieving the costs of incorporating large amounts of memory local to the graphics accelerator or frame buffer.
AGP uses the PCI specification as an operational baseline, yet provides three significant performance extensions or enhancements to that specification. These extensions include a deeply pipelined read and write operation, demultiplexing of address and data on the AGP bus, and ac timing specifications for faster data transfer rates.
Since computer systems were originally developed for business applications including word processing and spreadsheets, among others, the bridge logic within such systems was generally optimized to provide the CPU with relatively good performance with respect to its access to main memory. The bridge logic generally provided relatively poor performance, however, with respect to main memory accesses by other devices residing on peripheral busses, and similarly provided relatively poor performance with respect to data transfers between the CPU and peripheral busses as well as between peripheral devices interconnected through the bridge logic.
Recently, however, computer systems have been increasingly utilized in the processing of various real time applications, including multimedia applications such as video and audio, telephony, and speech recognition. These systems require not only that the CPU have adequate access to the main memory, but also that devices residing on various peripheral busses such as an AGP bus and a PCI bus have fair access to the main memory. Furthermore, it is often important that transactions between the CPU, the AGP bus and the PCI bus be efficiently handled. The bus bridge logic for a modern computer system should accordingly include mechanisms to efficiently prioritize and arbitrate among the varying requests of devices seeking access to main memory and to other system components coupled through the bridge logic.
To optimize efficiency, some PCI devices including bus bridges support delayed transaction operations. In systems supporting delayed transaction operations, when a delayed cycle to/from main memory, I/O, or configuration space is initiated on a bus such as the PCI bus, the PCI device detects the cycle and, rather than completing the cycle on the peripheral bus, the bus interface unit terminates or retries the cycle on the PCI bus. This frees the PCI bus to accommodate transactions by other devices. The bus interface unit concurrently requests the data from the source (memory, I/O, configuration space) or delivers the data to the destination (memory, I/O, or configuration space) corresponding to the retried delayed transaction. Ultimately, the PCI master establishing the delayed transaction operation will reattempt the operation, at which time the bus interface unit can immediately provide read data from its buffer or immediately accept write data. More efficient use of the PCI bus can thereby be attained.
Inefficiencies, therefore, can occur during delayed read operations, however, if the master establishing the delayed read operation re-attempts the read prior to the data being read from main memory or available within the buffer of the bus interface. In such cases, the bus interface unit will typically again terminate or retry the re-attempted read cycle effectuated by the PCI bus master. These operations waste bandwidth of the PCI bus. Since the PCI arbiter is unaware of the pending delayed read operation many such premature re-attempts to read the data may be performed by the PCI master. Delayed write transactions often face a similar problem.
It would accordingly be desirable to provide a computer system which optimizes delayed transactions to thereby accommodate higher performance.